LOGIC IC

The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC245; 74HCT245 is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The U74HC164 is an 8-bit edge-triggered shift registers with serial input and parallel output. A LOW-to-HIGH transition on the CP will shifts the data one place to the right which is the logical AND of DSA and DSB. A LOW level on the MR will clear the registers asynchronously and force the outputs LOW

The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The 74HC595 is an high speed CMOS device. An eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (SHCP). When asserted low the reset function ( ) sets all shift register values to zero and is indepent of all clocks. Data from the input serial shift register is placed in the output register with a rising pulse on the storages resister clock (STCP). With the output enable ( E asserted low the 3-state outputs Q0-Q7 become active and present th All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the output register.

The HEF4093B is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

The LVT244A is a high-performance BiCMOS device built for 3.3V VCC operation. This is an octal buffer designed for driving bus lines. The device has two Output Enables (OE1, OE2), each of which regulates four of the three-state outputs.

These full adders perform the addition of two 4-bit binary numbers. The sum (∑) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion

We have all the products metioned below in stock
CD4067  CD4069  CD4071
CD4072  CD4073  CD4076
CD4077  CD4078  CD4093
CD4094

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working reg

All these products are available in DIP and SMD 

74LS365 Entire Series 74LS684 Entire Series
74LS374 Entire Series 74LS623 Entire Series
74LS378 Entire Series 74LS673 Entire Series
74LS390 Entire Series 74LS640 Entire Series
74LS373 Entire Series 74LS645 Entire Series
74LS377 Entire Series 74LS646 Entire Series
74LS30  Entire Series  74LS629 Entire Series
74LS42  Entire Series  74LS624 Entire Series
74LS43  Entire Series  74LS688 Entire Series
74LS423 Entire Series 74LS642 Entire Series
74LS598 Entire Series 74LS641 Entire Series
74LS597 Entire Series 74LS75   Entire Series
74LS596 Entire Series 74LS73  Entire Series
74LS595 Entire Series 74LS74  Entire Series
74LS594 Entire Series 74LS86  Entire Series
74LS593 Entire Series 74LS85  Entire Series
74LS592 Entire Series 74LS92  Entire Series
74LS590 Entire Series 74LS93  Entire Series
74LS540 Entire Series 74LS90  Entire Series
74LS541 Entire Series

The 74HC573N is a high speed Si gate CMOS device with an octal D type Transparent Latch and three states that is pin compatible with low power Schottky TTL LSTTL JEDEC Standard No 7A has been complied with in the specification The bus oriented octal D type transparent latch has independent D type inputs for each latch and three state true outputs All latches share a latch enable LE input and an output enable OE input Data from the Dn inputs enters the latches when LE is high Latch outputs change state whenever the matching D input changes when the latches are transparent in this situation When LE is low the latches save the data that was available at the D inputs a set up time before LE went from high to low

These octal buffers and line drivers have a pinout with inputs and outputs on opposing sides of the package and perform as well as SNx4HC541 devices. The layout of printed circuit boards is substantially facilitated by this configuration. A two-input NOR gate regulates the 3-state outputs. All eight outputs are in the high-impedance state if any of the output-enable inputs (OE1 or OE2) is high. The outputs of the SNx4HC541 devices deliver genuine data.

Four separate 2-input XOR gates are present in this gadget. Each gate does the positive logic Boolean operation Y = A⊕B.
Features 
• Buffering of inputs.
•Large 2 V to 6 V operational voltage range.
-40°C to +85°C is a wide operational temperature range.
•Fanout up to 10 LSTTL loads are supported.
• Considerable power savings over LSTTL logic ICs.
Applications
• Recognise phase inconsistencies in incoming signals.
•Build an adjustable inverter/buffer.

Triple 3 Input AND Gate 74LS11 Basic Information There are three separate gates in this device each of which performs the logic AND operation 7V Supply Voltage 7V input voltage Operating Free Air Temperature 0 to 70 C Range of Storage Temperatures 65 C to 150 C

The HEF4094B-Q100 is an 8-bit shift register with 3-state outputs, a storage register, and serial/parallel input/output capabilities. There are separate clocks for the shift and storage registers. To facilitate cascading, the device has two serial outputs (QS1 and QS2) and a serial input (D). On the LOW-TO-HIGH transitions of the CP input, data is displaced. For cascade when clock edges are rapid, data on the LOW–TO–HIGH transitions of the CP input is accessible at QS1. The identical information is accessible at QS2 at the subsequent HIGH-TO-LOW transition of the CP input, enabling cascading in the event of delayed clock edges. When the STR input is HIGH, the data in the shift register is moved to the storage register. 

The pinout of the LS00 and the 74HC02 are identical The device inputs are compatible with LSTTL outputs without pullup resistors and Standard CMOS outputs without them Features 10 LSTTL Loads are supported by the output drive Outputs interface CMOS NMOS and TTL directly 2 0 to 6 0 V operating voltage range 1 0 A Low Input Current CMOS Devices Have a High Noise Immunity Characteristic Meets the requirements of JEDEC Standard No 7A Performance of the ESD HBM 2000 V and Machine Model 200 V Chip Complexity 8 Equivalent Gates or 32 FETs These devices don t contain pb

In order to increase the performance and density of three state memory address drivers clock drivers and bus oriented receivers and transmitters the SNx4LS24x SNx4S24x octal buffers and line drivers were particularly created The designer can choose from a variety of combinations of complementary output control GandG inputs symmetrical active low outputcontrol G inputs and inverting and noninverting outputs These gadgets have high fan out better fan in and 400 mV noise margin To drive terminated lines as low as 133 utilise the SN74LS24x and SN74S24x devices

shift register with 8 bits of parallel in and serial output 8 bit serial or parallel in serial out shift registers like the 74HC165 and 74HCT165 are available Eight parallel data inputs D0 to D7 a serial data input DS and two complementary serial outputs Q7 and Q7 are all elements of the device The data from D0 through D7 is loaded into the shift register asynchronously when the parallel load input PL is LOW Data enters the register serially at DS while PL is HIGH The data is shifted on the LOW to HIGH transitions of the CP input when the clock enable input CE is LOW The CP input will be disabled by a HIGH on CE Overvoltage tolerance for inputs is 15 V Due to this the device can be utilised for applications involving HIGH TO LOW level changing