Memory Ic

All members of the 26 Series, SQI family are manufactured with proprietary, high-performance CMOS SuperFlash® technology. The split-gate cell design and thickoxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.

The SST25VF016B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for SST25VF016B. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies.  

The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro-grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bitseach. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applica-tions where low power and low voltage operation are essential. The AT24C32/64 isavailable in space saving 8-pin JEDEC PDIP, 8-pin and 14-pin JEDEC SOIC, 8-pinEIAJ SOIC, and 8-pin TSSOP packages and is accessed via a 2-wire serial interface.In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions

The AT93C46/56/57/66 provides 1024/2048/4096 bits of serial electrically erasableprogrammable read only memory (EEPROM) organized as 64/128/256 words of 16bits each, when the ORG Pin is connected to VCC and 128/256/512 words of 8 bitseach when it is tied to ground. The device is optimized for use in many industrial andcommercial applications where low power and low voltage operations are essential.The AT93C46/56/57/66 is available in space saving 8-pin PDIP and 8-pin JEDEC andEIAJ SOIC packages

ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.